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1 www.semtech.com SC2440 2.5 mhz dual switching regulator with integrated 2a switches power management revision: march 5, 2007 description features applications typical application circuit u up to 2.5 mhz/channel programmable switching frequency u fixed frequency current-mode control u wide input voltage range 2.8v to 20v u out of phase switching reduces ripple u cycle-by-cycle current-limiting u independent shutdown/soft-start pins u independent hiccup overload protection u independent power-good indicators u two 2a integrated switches u external synchronization u thermal shutdown u thermally enhanced 16-pin tssop package the SC2440 is an adjustable frequency dual current- mode switching regulator with 2a integrated switches. its high frequency operation allows the use of small inductors and capacitors, resulting in very compact power supplies. the SC2440 is suitable for next generation xdsl modems requiring operating frequencies in excess of 1.5 mhz. the two channels operate at 180 out of phase for reduced input voltage ripples. separate soft start/ shutdown pins allow independent control and output sequencing for latch-up prevention. the SC2440 can also be externally synchronized up to 2.5 mhz per channel. current-mode pwm control allows fast transient response with simple loop compensation. cycle-by-cycle current limiting and hiccup overload protection reduce power dissipation during overload. u xdsl and cable modems u set-up boxes u point of load applications u cpe equipment u dsp power supplies u disk drives c15 10 m f r3 40.2k SC2440 gnd ss2 in sw1 fb2 rosc comp2 c9 10p f r7 24.3k boost1 c1 10 m f boost2 sw2 l1 3.3 m h c2 0.1 m f l2 4.4 m h c4 0.1 m f pgood2 ss1 pgood1 comp1 fb1 c3 10 m f d1 ups120 d2 ups120 r8 100k r6 100k r9 15k out1 3.3v/2a 10k r4 10k r2 r1 23.3k c7 22n f c10 22n f c8 220p f c6 10p f r5 15.4k c5 470p f d4 1n4148 sync l1: sumida cr43 l2: falco d04012 out2 5v/2a d3 1n4148 vin 12v efficiency vs load current figure 1. 1.3mhz 12v to 3.3v and 5v step-down converter 50 55 60 65 70 75 80 85 90 95 0 0.5 1 1.5 2 load current (a) efficiency (%) v out2 = 5v v out1 = 3.3v v in = 12v
2 ? 2005 semtech corp. www.semtech.com sc2 440 power management absolute maximum ratings electrical characteristics exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of the parameters specified in the electrical characteristics section is not implied. parameter symbol max units input voltage v in -0.3 to 20 v boost pin v bst 40 v boost pin above sw v bst -v sw 20 v pgood pin voltage v pgood v in v ss pins v ss 3 v fb pins v fb -0.3 to v in v sync pin current i sync 5 ma sw voltage v sw -0.6 to v in v sw transient spikes (<10ns duration) v sw v in +1.5 v -2.5 operating ambient temperature range t a -40 to 85 c thermal resistance junction to ambient q ja 45 c/w maximum junction temperature t j 150 c storage temperature range t stg -65 to +150 c lead temperature (soldering)10 sec t lead 300 c parameter conditions min typ max units v in start voltage 2.45 2.62 2.78 v v in start hysteresis 75 mv quiescent current not switching, pgood open 3.3 4.3 ma shutdown current v ss1 = v ss2 = 0v, pgood open 38 60 a feedback voltage 0.980 1.000 1.020 v feedback voltage line regulation v in = 3v to 20v 0.005 %/v fb pin input bias current v fb = 1v, v comp = 1.5v -15 -30 na error amplifier transconductance 280 w -1 error amplifier open-loop gain 53 db comp source current v fb = 0.8v, v comp = 1.5v 20 a comp sink current v fb = 1.2v, v comp = 1.5v 20 a comp pin to switch current gain 5.7 a/v unless specified: - 40c < t a < 85c, - 40c < t j < 105c, r osc = 12.1k w , v sync = 0, v in = 5v, v boost = 8v
3 ? 2005 semtech corp. www.semtech.com sc2 440 power management electrical characteristics (cont.) unless specified: - 40c < t a < 85c, - 40c < t j < 105c, r osc = 12.1k w , v sync = 0, v in = 5v, v boost = 8v parameter conditions min typ max units comp switching threshold 0.7 1.1 1.3 v comp maximum voltage v fb = 0.9v 2.2 v channel switching frequecy 1.2 1.4 1.6 mhz maximum duty cycle (note 2) 80 90 % switch current limit v fb = 0.9v, v ss = 2.3v, comp pin open 2 2.6 a switch saturation voltage i sw = -2a 0.3 0.48 v switch leakage current 10 a minimum boost voltage i sw = -2a 1.8 2.5 v boost pin current i sw = -0.5a 20 30 ma i sw = -2a 60 80 ma minimum soft-start voltage to exit shutdown ss1 tied to ss2 0.2 0.4 0.7 v soft-start charging current v ss = 0v 2 a v ss = 1.5v 1.8 a soft-start discharging current v ss = 1.5v 0.8 a minimum soft-start voltage to enable overload shutoff v ss rising 2 v fb overload threshold v ss = 2.3v, v fb falling 0.74 v soft-start voltage to restart switching after overload shutoff v ss falling 0.7 1 1.3 v power good threshold below fb v fb rising 80 100 120 mv power good output low voltage v fb = 0.8v, i pgood = 250a 0.2 0.4 v power good pin leakage current v pgood = 5v 0.1 1 a sync input high voltage 2 v sync input low voltage (note 1) 0.8 v sync frequency sync frequency = 2 x channel frequency. (note 1) 3.4 5 mhz sync pin input current v sync = 2v 60 75 a thermal shutdown temperature 155 c thermal shutdown hysteresis 10 c notes: (1) guaranteed by design, not tested in production. (2) the maximum duty cycle specified corresponds to 1.4mhz switching frequency. duty cycles higher than those specified can be achieved by lowering the operating frequency. (3) this device is esd sensitive. use of standard esd handling precautions is required.
4 ? 2005 semtech corp. www.semtech.com sc2 440 power management pin configuration ordering information underside metal must be soldered to ground. pin # pin name pin function 1, 8 boost1, boost2 supply pins to the power transistor drivers.tie to external diode-capacitor charge pumps to generate drive voltages higher than v in in order to fully saturate the internal npn power switches. 2, 7 sw1, sw2 emitters of the internal power npn transistors. connect to the inductors, the freewheeling diodes and the boost capacitors. 3, 6 in input power supply pins of the SC2440 and also the common collector of the internal power npns. pins 3 and 6 are internally tied together and must be locally bypassed. 4 sync driving the sync pin with an external clock synchronizes both step-down converters. the external clock frequency must be at least twice the individual regulator set (or free-running) frequency. tie this pin to ground if not used. 5 rosc an external resistor between this pin and the ground sets the master oscillator free-running frequency. the set frequency is twice that of the individual switching regulator. 9, 16 fb1, fb2 the inverting inputs of the error amplifiers. each fb pin is tied to a resistive divider between its output and the ground for setting the channel output voltage. 10, 15 comp1, comp2 these are the outputs of the internal error amplifiers. the voltages on these pins control the peak switch currents. rc networks at these pins compensate the control loops. pulling either pin below 0.7v stops the corresponding switching regulator. 11, 14 pgood1, pgood2 open collector outputs of the power good comparators. tie to external pull-up resistors from the input or the output of the converter. the pgood outputs become valid as soon as v in rises above 1 v be during power-up. pgood is actively pulled low until the corresponding fb pin rises to within 10% of the final regulation voltage. 12, 13 ss1, ss2 a capacitor from either ss pin to the ground provides soft-start and overload hiccup functions for that channel. pulling either ss pin below 0.8v with an open drain or collector transistor shuts off the corresponding regulator. to completely shut off the SC2440 to low-current state, pull both ss pins to the ground. soft-start is recommended for all applications. underside metal gnd the exposed pad at the bottom of the package is the electrical ground connection of the SC2440. it also provides a thermal contact to the circuit board. it is to be soldered to the ground plane of the board. pin descriptions part number package (1)(2) SC2440tetrt tssop-16 edp SC2440evb evaluation board notes: (1) only available in tape and reel packaging. a reel contains 2500 devices. (2) lead free product. this product is fully weee and rohs compliant. 1 2 3 4 5 6 7 8 fb1 boost1 top view (16 pin tssop - edp) 13 12 14 15 16 11 10 9 comp1 sw1 pgood1 in ss1 sync ss2 rosc pgood2 in comp2 sw2 fb2 boost2
5 ? 2005 semtech corp. www.semtech.com sc2 440 power management block diagrams pgood1 comp1 transistor rosc in 3 fb1 sw1 ea r q s pwm - + + - power slope comp 1 + + + - isen ilim + - 20mv s s 7.7m w boost1 ss1 oscillator clk2 clk1 frequency divider slope comp sync slope comp 2 slope comp 1 ss2 reference & thermal shutdown 1v fault ovld soft - start and overload hiccup control 1 0.74v fb1 power good - + 100mv 1 2 16 5 4 12 13 15 14 figure 2. SC2440 functional diagram (one of two converters shown) fault ss ovld 1v/2v s q r + - 1.8 m a 2.6 m a fb 0.74v figure 3. details of the soft-start and overload hiccup control circuit
6 ? 2005 semtech corp. www.semtech.com sc2 440 power management typical characteristics frequency setting resistor vs channel frequency 1 10 100 1000 0 0.5 1 1.5 2 2.5 3 frequency (mhz) r osc (k w w ) v in = 5v feedback voltage vs temperature 0.97 0.98 0.99 1.00 1.01 1.02 -50 -25 0 25 50 75 100 125 temperature (c) v fb (v) v in = 5v switch saturation voltage vs switch current 100 200 300 400 0.0 0.5 1.0 1.5 2.0 2.5 switch current (a) v cesat (mv) 25c 125c -40c v in start threshold vs temperature 2.4 2.5 2.6 2.7 2.8 -50 -25 0 25 50 75 100 125 temperature (c) v in threshold (v) sync input logic thresholds vs temperature 1.0 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 temperature (c) sync thresholds (v) v ih v il channel frequency vs temperature 1.2 1.3 1.4 1.5 1.6 -50 -25 0 25 50 75 100 125 temperature (c) frequency (mhz) r osc =12.1k w ss shutdown threshold vs temperature 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 temperature (c) ss threshold (v) v ss1 = v ss2 boost pin current vs switch current 0 20 40 60 80 0.0 0.5 1.0 1.5 2.0 2.5 switch current (a) boost pin current (ma) 125c -40c v in = 5v v bst = 8v switch current limit vs temperature 2.0 2.2 2.4 2.6 2.8 3.0 -50 -25 0 25 50 75 100 125 temperature (c) current limit (a)
7 ? 2005 semtech corp. www.semtech.com sc2 440 power management typical characteristics soft-start pin current vs soft-start voltage -120 -100 -80 -60 -40 -20 0 0.0 0.5 1.0 1.5 2.0 v ss (v) i ss ( m m a) i ss of the other channel (v ss = 0) i ss of the swept channel t = 25c v in =5v fb overload threshold vs temperature 0.5 0.6 0.7 0.8 0.9 1.0 -50 -25 0 25 50 75 100 125 temperature (c) fb threshold (v) v in quiescent current vs v in 0 1 2 3 4 0 5 10 15 20 v in (v) v in current (ma) 25c -40c 105c v in shutdown current vs v in 0 25 50 75 100 125 150 0 5 10 15 20 v in (v) v in current ( m m a) 105c -40c ss1 = ss2 = 0 pgood threshold to feedback difference voltage vs temperature -100 -98 -96 -94 -92 -90 -50 -25 0 25 50 75 100 125 temperature (c) voltage (mv) v in supply current vs soft-start voltage 0 1 2 3 4 0.0 0.5 1.0 1.5 2.0 v ss (v) i in (ma) v ss1 = v ss2 t a = 25c v in = 5v v comp1 = 0 v comp2 = 0
8 ? 2005 semtech corp. www.semtech.com sc2 440 power management operation the SC2440 is a 2-channel constant-frequency peak current-mode step-down switching regulator with integrated 2a power transistors. both regulators of the SC2440 operate from a common input power supply and share the same voltage reference, the master oscillator and the synchronizing circuit. turn-on of the power transistors are phase-shifted by 180 . the two regulators are otherwise completely identical, independent and are capable of producing two separate outputs from the same input. the master oscillator of the SC2440 runs at twice the channel frequency. the free-running frequency of the master oscillator can be programmed with an external resistor from the rosc pin to ground. frequency adjustability makes switching regulator design flexible. peak current-mode control is utilized for the SC2440. the double reactive poles of the output lc filter are reduced to a single real pole by the inner current loop, easing loop compensation. fast transient response can be achieved with a simple type-2 compensation network. switch collector current is sensed with an integrated 7.7m w sense resistor. the sensed current is summed with slope- compensating ramp before it is compared with the transconductance error amplifier output. the pwm comparator tripping instant determines the switch turn- on pulse width (figure 2). the current-limit comparator ilim turns off the power switch when the sensed-signal exceeds the 20mv current-limit threshold. ilim therefore provides cycle-by-cycle limit. current-limit does not vary with duty-cycle. driving the base of the power transistor above the input power supply rail minimizes the power transistor turn-on voltage and maximizes efficiency. an external charge pump (formed by the capacitor c 2 and the diode d 3 in figure 1) generates a voltage higher than the input rail at the boost pin. the bootstrapped voltage generated becomes the supply voltage for the power transistor driver. the ss pin is a multiple-function pin. an external capacitor connected from the ss pin to the ground together with the internal 1.8a and 2.6a current sources set the soft-start and overload shutoff times of the regulator (figure 3). the ss pin can also be used to shut off the corresponding regulator. when either ss pin is pulled below 0.8v, that regulator is turned off. if both ss pins are pulled below 0.2v, then the SC2440 undergoes overall shutdown. the current draw from the input power supply reduces to 38a. when either ss pin is released, the corresponding soft- start capacitor is charged with a 2a current source (not shown in figure 3). as either ss voltage exceeds 0.3v, the internal bias circuit of the SC2440 is enabled. the SC2440 draws 3.3ma from v in . an internal fast charge circuit quickly charges the soft-start capacitor to 1v. at this juncture, the fast charge circuit turns off and the 1.8a current source slowly charges the soft-start capacitor. the output of the error amplifier is forced to track the slow soft-start ramp at the ss pin. when the comp voltage exceeds 1.1v, the switching regulator starts to switch. during soft-start, the current limit of the converter is gradually increased until the converter output comes into regulation. hiccup overload protection is utilized in the SC2440. overload shutdown is disabled during soft-start (v ss < 2v). in figure 3 the reset input of the overload latch will remain high if the ss voltage is below 2v. once the soft- start capacitor is charged above 2v, the overload shutdown latch is enabled. as the load draws more current from the regulator, the current-limit comparator will limit the peak inductor current. this is cycle-by-cycle current limiting. further increase in load current will cause the output voltage to decrease. if the output voltage falls below 74% of its set point, then the overload latch will be set and the soft-start capacitor will be discharged with a net current of 0.8a. the switching regulator is shut off until the soft-start capacitor is discharged below 1v. at this moment, the overload latch is reset. the soft-start capacitor is recharged and the converter again undergoes soft-start. the regulator will go through soft-start, overload shutdown and restart until it is no longer overloaded. each regulator of the SC2440 has its own power good comparator. the open collector output of the power good comparator will be actively pulled low if the corresponding feedback voltage is below 0.9v.
9 ? 2005 semtech corp. www.semtech.com SC2440 power management applications information setting the output voltage the regulator output voltage is set with an external resistive divider (figure 4) with its center tap tied to the fb pin. ) 1 v ( r r out 2 1 ? = (1) the percentage error due the input bias current of the error amplifier is v 1 ) r r ( 100 na 15 v v 2 1 out out ?? ? ? ? = ? . example: determine the output voltage error of a v 5 v out = converter with ? = k 1 . 51 r 2 . from (1), ? = ? ? ? = k 205 ) 1 5 ( k 1 . 51 r 1 % 061 . 0 v 1 ) k 205 k 1 . 51 ( 100 na 15 v v out out ? = ?? ? ? ? = ? . this error is at least an order of magnitude lower than the ratio tolerance resulting from the use of 1% resistors in the divider string. choosing the operating frequency the free-running frequency of the master master master master master oscillator is set with an external resistor from the rosc pin to ground. channel frequency is one-half of that of the master oscillator. a graph of channel channel channel channel channel freq uency against r osc is shown in the ?typical performance characteristics?. before choosing the operating frequency, tradeoffs among efficiency, operating duty cycle, component size and emi interferences must be considered. high frequency operation reduces the size of passive components but switching losses are higher. lowering the switching frequency improves efficiency. however the required inductor and capacitor are larger. channel frequencies between 1 and 2mhz are good compromises. in order to quantify the tradeoff between switching frequency and efficiency, the 12v to 5v dc-dc converter in figure 1 is modified to run at 500khz and 2.5mhz while keeping the inductor ripple current constant. the modified component values are tabulated in table 1 and efficiencies at these frequencies are shown in figure 5. the efficiency of the 1.3mhz 5v regulator in figure 1 is also plotted for the ease of comparison. the efficiency at 500khz is only marginally higher than that at 1.3mhz. the peak efficiency at 2.5mhz is only 2% lower compared to those at lower frequencies. vout r2 r1 15na fb SC2440 figure 4. v out is set with a resistive divider f ) z h m (r 9 k ( ? )l 2 ( ) hr 7 k ( ? )c 8 ) f p (c 9 ) f p ( 5 . 06 . 3 5) 0 0 1 - 3 7 r d s c i n o r t l i o c ( 0 14 . 2 10 7 42 2 3 . 10 . 5 1) 2 1 0 4 0 d o c l a f ( 4 4 . 43 . 4 20 2 20 1 5 . 22 0 . 4) 7 r 2 - 3 4 r c a d i m u s ( 7 . 24 . 2 30 2 20 1 table 1. the 12v to 5v converter in figure 1 is modified to run at different frequencies. efficiency vs load current 75 80 85 90 0.0 0.5 1.0 1.5 2. 0 load current (a) efficiency (%) v in =12v v out =5v 2.5mhz 1.3mhz 500khz figure 5. efficiencies of 500khz, 1.3mhz and 2.5mhz 12v to 5v step-down converters.
10 ? 2005 semtech corp. www.semtech.com sc2 440 power management minimum on time consideration the operating duty cycle of a step-down switching regulator with diode rectifier in continuous-conduction mode (ccm) is given by cesat d in d out v v v v v d - + + = (2) where v cesat is the switch saturation voltage and v d is voltage drop across the rectifying diode. duty cycle decreases with increasing out in v v ratio. in peak current-mode control, the pwm modulating ramp is the sensed current ramp of the power switch. this current ramp is absent unless the switch is turned on. the intersection of this ramp with the output of the voltage feedback error amplifier determines the switch pulse width. the propagation delay time required to immediately turn off the switch after it is turned on is the minimum switch on time (t on (min) ). closed-loop measurement of the SC2440 with low in out v v ratios shows that the minimum on time is about 105ns at room temperature. t on (min) also exhibits a slight positive temperature coefficient (figure 6). the power switch in the SC2440 is either not turned on at all or for at least t on (min) . if the required switch on time (= f d ) is shorter than the minimum on time, the regulator will either skip cycles or it will jitter. example: determine the maximum operating frequency of a dual 12v to 1.0v and 12v to 3.3v switching regulator using the SC2440. assuming that v d = 0.45v, v cesat = 0.25v and v in = 13.2v (10% high line), the corresponding duty ratios, d 1 and d 2 , of the 1.0v and 3.3v converters can be calculated using (2). 11 . 0 25 . 0 45 . 0 2 . 13 45 . 0 1 d 1 = - + + = applications information 28 . 0 25 . 0 45 . 0 2 . 13 45 . 0 3 . 3 d 2 = - + + = if the ambient temperature can be as high as 85 c, then the maximum operating frequencies of the 1.0v and the 3.3v converters will be khz 920 ns 120 d 1 = and mhz 3 . 2 ns 120 d 2 = respectively. . channel frequency should be set below 920khz to allow margin for load transient. minimum off time limitation the pwm latch in figure 2 is reset every period by the clock. the clock also turns off the power transistor to refresh the bootstrap capacitor. this minimum off time limits the attainable duty cycle of the regulator at a given switching frequency. measurement shows that the power transistor needs to be turned off for at least 120ns every switching period to properly reset the latch and to refresh the bootstrap capacitor. for a step-down converter, d increases with increasing in out v v ratio. if the required duty cycle is higher than the attainable maximum, then the figure 6. variation of minimum on time with temperature. minimum on time vs temperature 80 90 100 110 120 130 -40 -20 0 20 40 60 80 100 temperature (c) t on(min) (ns)
11 ? 2005 semtech corp. www.semtech.com sc2 440 power management output voltage will not be able to reach its set value in continuous-conduction mode. example : determine the maximum operating frequency of a dual 3.3v to 1.8v and 3.3v to 2.5v switching regulator using the SC2440. assuming that v d = 0.45v, v cesat = 0.25v and v in = 2.97v (10% low line), the duty ratios 1 d and 2 d of the 1.8v and 2.5v converters can be calculated using (2). 71 . 0 25 . 0 45 . 0 97 . 2 45 . 0 8 . 1 d 1 = - + + = 93 . 0 25 . 0 45 . 0 97 . 2 45 . 0 5 . 2 d 2 = - + + = . the maximum operating frequencies of the 1.8v and the 2.5v converters are therefore mhz 4 . 2 ns 120 d 1 1 = - and khz 580 ns 120 d 1 2 = - respectively. . transient headroom requires that channel frequency be lower than 580khz. external synchronization the sync input buffer is positive-edge triggered and ttl- compatible ( v 8 . 0 v il < and v 2 v ih > ). the free-running master oscillator generates a periodic sawtooth ramp between two threshold voltages. a faster external clock applied to the sync pin discharges the internal ramp before it reaches its upper threshold, thus locking the internal oscillator. as shown in figure 2, the master oscillator is being synchronized not the individual phases (see figure 2). the synchronizing frequency should be twice twice the desired channel channel frequency. bench test shows that an external clock with frequency ranging from slightly below twice to at least 3.5 times the channel channel free- running frequency is capable of locking the master oscillator. to ensure frequency locking, the external clock frequency should be at least twice twice the highest highest free- running channel channel frequency. the frequency of the synchronizing clock should not be higher than 1.6 times applications information the set frequency of master oscillator because the amplitudes of the internal sawtooth ramp and slope compensation ramp will both be significantly reduced. example: choose the value of r osc to externally synchronize the SC2440 to 2mhz per channel channel . the required synchronizing clock frequency = 2 times the channel frequency = 4mhz. for a given r osc , the free-running channel channel frequency has a tolerance of 15%. set the nominal free-running channel channel frequency to mhz 73 . 1 15 . 1 mhz 2 = to ensure locking. looking up the graph ?channel frequency vs. r osc ? in the typical characteristics, r osc = 9.31k w for a set frequency of 1.73mhz. with 15% tolerance, the set channel frequency can vary from ( ) mhz 47 . 1 73 . 1 85 . 0 = to ( ) mhz 2 73 . 1 15 . 1 = . therefore 36 . 1 47 . 1 2 frequency running free lowest frequency ing synchroniz = = - . inductor selection the inductor ripple current d i l for a non-synchronous step-down converter in continuous-conduction mode is fl ) v v v ( ) v v v )( v v ( fl ) d 1 )( v v ( i cesat d in cesat out in d out d out l - + - - + = - + = d (3) where f is the switching frequency and l is the inductance. in current-mode control, the slope of the modulating (sensed switch current) ramp should be steep enough to lessen jittery tendency but not so steep that large flux swing decreases efficiency. inductor ripple current d i l between 25-40% of the peak inductor current limit is a good compromise. inductors so chosen are optimized
12 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information in size and dcr. setting a 6 . 0 ) 2 ( 3 . 0 i l = = d , v 45 . 0 v d = and v 25 . 0 v cesat = in (3), f ) 6 . 0 )( 2 . 0 v ( ) 25 . 0 v v )( 45 . 0 v ( l in out in out + - - + = (4) where l is in m h and f is in mhz. equation (3) shows that for a given , v out l i d increases as d decreases. if in v varies over a wide range, then choose l based on the nominal input voltage. always verify converter operation at the input voltage extremes. the peak current limits of both SC2440 power transistors are internally set at 2.6a. the peak current limits are duty-cycle invariant and are guaranteed higher than 2a. the maximum load current is therefore conservatively 2 i a 2 2 i i i l l lm ) max ( out d - = d - = (5) if lm l i 3 . 0 i = d , then lm lm lm l lm ) max ( out i 85 . 0 2 i 3 . 0 i 2 i i i = - = d - = . the saturation current of the inductor should be 20-30% higher than the peak current limit (2a). low-cost powder iron cores are not suitable for high-frequency switching power supplies due to their high core losses. inductors with ferrite cores should be used. input capacitor a buck converter draws pulse current with peak-to-peak amplitude equal to its output current i out from its input supply. an input capacitor placed between the supply and the buck converter filters the ac current and keeps the current drawn from the supply to a dc constant. the input capacitance c in should be high enough to filter the pulse input current. its equivalent series resistance (esr) should be low so that power dissipated in the capacitor does not result in significant temperature rise and degrade reliability. for a single channel buck converter, the rms ripple current in the input capacitor is ) d 1 ( d i i out rms ) cin ( - = . (6) power dissipated in the input capacitor is ) esr ( i 2 rms ) cin ( . equation (6) has a maximum value of 2 i out ( at 2 1 d = ), corresponding to the worst-case power dissipation 4 esr i 2 out in c in . a dual-channel step-down converter with interleaved switching reduces the rms ripple current in the input capacitor to a fraction of that of a single-phase buck converter. if both power transistors in the SC2440 were to switch on in phase, the current drawn by the SC2440 would consist of current pulses with amplitude equal to the sum of the channel output currents. if each channel were delivering i out and operating at 50% duty cycle, then the input current would switch from zero to 2i out . the rms ripple current in the input capacitor would then be i out . power dissipated in c in would be esr i 2 out , 4 times that of a single-channel converter. the SC2440 produces the highest rms ripple current in c in when only one channel is running and delivering the maximum output current ( a 2 5 . 1 - ? ) . the input capacitor therefore should have a rms ripple current rating of at least 1a. multi-layer ceramic capacitors, which have very low esr (a few m w ) and can easily handle high rms ripple current, are the ideal choice for input filtering. a single 4.7 m f or 10 m f x5r ceramic capacitor is adequate. for high voltage applications, a small ceramic (1 m f or 2.2 m f) can be placed in parallel with a low esr electrolytic capacitor to satisfy both the esr and bulk capacitance requirements. output capacitor the output ripple voltage d v out of a buck converter can be expressed as ? ? ? ? ? + d = d out l out fc 8 1 esr i v (7) where c out is the output capacitance. inductor ripple current d i l increases as d decreases (equation (3)). the output ripple voltage is therefore the highest when v in is at its maximum. the first term in (7)
13 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information results from the esr of the output capacitor while the second term is due to the charging and discharging of c out by the inductor ripple current. substituting d i l = 0.6a, f = 1mhz and c out = 10 m f ceramic with esr = 3m w in (7), mv 3 . 9 mv 5 . 7 mv 8 . 1 ) m 5 . 12 m 3 ( a 6 . 0 v out = + = w + w = d depending on operating frequency and the type of capacitor, ripple voltage resulting from charging and discharging of c out may be higer than that due to esr. a 10 m f or 22 m f x5r ceramic capacitor is found adequate for output filtering in most applications. ripple current in the output capacitor is not a concern because the inductor current of a buck converter directly feeds c out , resulting in very low ripple current. avoid using z5u and y5v ceramic capacitors for output filtering because these types of capacitors have high temperature and high voltage coefficients. freewheeling diode use of schottky barrier diodes as freewheeling rectifiers reduces diode reverse recovery input current spikes, easing high-side current sensing in the SC2440. these diodes should have a rms current rating between 1a and 2a and a reverse blocking voltage of at least 5v higher than the input voltage. for switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is beneficial to use freewheeling diodes with somewhat higher rms current ratings (thus lower forward voltages). this is because the diode conduction interval is much longer than that of the transistor. converter efficiency will be improved if the voltage drop across the diode is lower. the freewheeling diodes should be placed close to the sw pins of the SC2440 to minimize ringing due to trace inductance. surface-mount equivalents of 1n5817 and 1n5819, mbrm120lt3 (on semi), ups120 and ups140 (micro-semi) are all suitable. bootstrapping the power transistors to maximize efficiency, the turn-on voltage across the internal power npn transistors should be minimized. if these transistors are to be driven into saturation, then their bases will have to be driven from a power supply higher in voltage than v in . the required driver supply voltage (at least 2.5v higher than the sw voltage over the industrial temperature range) is generated with a bootstrap circuit (the diode d bst and the capacitor c bst in figure 8). the bootstrapped output (the common node between d bst and c bst ) is connected to the boost pin of the SC2440. the power transistor in the SC2440 is first switched on to build up current in the inductor. when the transistor is switched off, the inductor current pulls the sw node low, allowing c bs t to be charged through d bs t . when the power switch is again turned on, the sw voltage goes high. this brings the boost voltage to bst c sw v v + , thus back-biasing d bs t . c bs t voltage increases with each subsequent switching cycle, as does the bootstrapped voltage at the boost pin. after a number of switching cycles, c bst will be fully charged to a voltage approximately equal to that applied to the anode of d bst . figure 7 shows the typical minimum boost to sw voltage required to fully saturate the power transistor. this differential voltage ( bst c v = ) must be at least 1.8v at room temperature. this is also specified in the ?electrical characteristics? as ?minimum bootstrap voltage?. the minimum required v c bst increases as temperature decreases. the bootstrap circuit reaches equilibrium when the base charge drawn from c bst during transistor on time is equal to the charge replenished during the off interval. figure 7. typical minimum bootstrap voltage re- quired to maintain saturation at i sw = 2a. minimum bootstrap voltage vs temperature 1.4 1.6 1.8 2.0 2.2 2.4 -50 -25 0 25 50 75 100 temperature (c) voltage (v)
14 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information the switch base current a i 1 a i sw sw ? + = , where i sw and b are the switch emitter current and current gain respectively, is drawn from the bootstrap capacitor c bst . charge a t i on sw is drawn from c bst during the switch on time, resulting in a voltage droop of bst on sw ac t i . if i sw = 2a, t on = 1 m s, b = 35 and c bst = 0.1 m f, then the bst c v droop will be 0.57v. c bst is refreshed to rect bst d d a v v v + - every y cycle, where a v is the applied d bst anode voltage. switch base current discharges the bootstrap capacitor to bst on sw d d a c t i v v v rect bst b - + - at the end of conduction. the difference between this voltage and that at sw must be higher than the minimum shown in figure 7 to maximize efficiency. d bst can be tied either to the input or to the output of the dc/dc converter. if d bst is tied to the input, then the charge drawn from the input power supply will be b on sw t i (the base charge of the switch). the energy loss due to base charge per cycle is b on in sw t v i for a power loss of b ? b out sw in sw v i v di . if d bst is tied to the output, then the charge drawn from the output capacitor will still be b on sw t i . the energy loss due to base charge per cycle is b on out sw t v i for a power figure 8. methods of bootstrapping the SC2440. max v bst = 2v i n max v bst = v i n + v out max v bst = v i n + v s max v bst = v s (a) SC2440 boost gnd in sw dbst vout cbst vin d rect (b) SC2440 boost gnd in sw dbst vout cbst vin d rect (d) SC2440 boost gnd in sw dbst vout vin vs > vin + 2.5v d rect SC2440 boost gnd in sw dbst vout cbst vin vs > 2.5v (c) d rect
15 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information loss of b out sw v di . since v out < v in , d bst should always be tied to v out (if >2.5v) to maximize efficiency. measurement of the 2- channel regulator in figure 1 shows that the efficiency penalties are about 1.3% (v out = 5v) and 2.2% (v out = 3.3v) with input bootstrapping. in general efficiency penalty increases as d decreases. figure 8 summarizes various ways of bootstrapping the SC2440. a fast switching pn diode (such as 1n4148 or 1n914) and a small (0.1f ? 0.47f) ceramic capacitor can be used. in figure 8(a) the power switch is bootstrapped from the output. this is the most efficient configuration and it also results in the least voltage stress at the boost pin. the maximum boost pin voltage is about out in v v + . if the output is below 2.8v, then d bst t will preferably be a small schottky diode (such as bat- 54) to maximize bootstrap voltage. a 0.33-0.47f bootstrap capacitor may be needed to reduce droop. bench measurement shows that using schottky bootstrapping diode has no noticeable efficiency benefit. the SC2440 can also be bootstrapped from the input (figure 8(b)). this configuration is not as efficient as figure 8(a). however this may be only option if the output voltage is less than 2.5v and there is no other supply with voltage higher than 2.5v. voltage stress at the boost pin can be somewhat higher than 2 v in . the boost pin voltage should not exceed its absolute maximum rating of 40v. figures 8(c) and (d) show how to bootstrap the SC2440 from a second independent power supply v s with voltage > 2.5v. d bst in figure 8(d) prevents start up difficulty if v in comes up before v s . since the inductor current charges c bst , the bootstrap circuit requires some minimum load current to get going. figures 9(a) and 9(b) show the dependence of the minimum input voltage required to properly bootstrap a 5v and a 3.3v converters on the load current. once started the bootstrap circuit is able to sustain itself down to zero load. shutdown and soft-start each regulating channel of the SC2440 has its own soft- start circuit. pulling its soft-start pin below 0.8v with an open-collector npn or an open-drain nmos transistor turns off the corresponding regulator. the other regulator continues to operate. with one channel turned off, the internal bias circuit is kept alive. in the ?typical characteristics?, the soft-start pin current is plotted against the soft-start voltage with v in = 5v . when one of figure 9. minimum input voltage required to start and to maintain bootstrap.(t a = 25 c). minimum starting and sustaining v in vs load current 4.5 5.0 5.5 6.0 6.5 7.0 7.5 1 10 100 1000 load current (ma) minimum input voltage (v) d bst tied to output d bst tied to input v out = 5v starting sustaining ma729 (a) (b) minimum starting and sustaining v in vs load current 3.5 4.0 4.5 5.0 5.5 0.1 1.0 10.0 100.0 1000.0 load current (ma) minimum input voltage (v) d bst tied to output d bst tied to input v out = 3.3v starting sustaining ma729
16 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information the soft-start pins is pulled low, 105a flows out of that pin. pulling both soft-start pins below 0.2v shuts off the internal bias circuit of the SC2440. the total v in current decreases to 38a. in shutdown either ss pin sources only 2a. a fast charging circuit (enabled by the internal bias circuit), which charges the soft-start capacitor below 1v, causes the difference in the soft-start pin currents. if either ss pin is released in shutdown, the internal current source pulls up on the ss pin. when this ss voltage reaches 0.3v, the SC2440 turns on and the v in quiescent current increases to 3.3ma. the current flowing out of the other ss pin (which is still pulled low) increases to 105a. the fast charging circuit quickly pulls the released soft-start capacitor to 1v (slightly below the switching threshold). the fast charging circuit is then disabled. a 1.8a current source continues to charge the soft-start capacitor (figure 3). the soft-start voltage ramp at the ss pin clamps the error amplifier output (figure 2). during regulator start-up, comp voltage follows the ss voltage. the converter starts to switch when its comp voltage exceeds 1.1v. the peak inductor current gradually increases until the converter output comes into regulation. proper soft-start prevents output overshoot during start-up. current drawn from the input supply is also well controlled. notice that the inductor current, not the converter output voltage, is ramped during soft-start. both soft-start capacitors are charged to a final voltage of about 2.4v. figure 10(a). normal soft-start. fast charge output must be at least 74% of its set voltage in this interval or the regulator will undergo shutdown and restart (hiccup). hiccup enabled 0.3v 1v 0 2v 2.4v switching starts v ss 1v 0.74v v fb 0 1v 1v 2v 0.3v 0 switching not switching switching not switching 0 0.74v 1v v fb v ss v comp figure 10(b). start-up fails due to (i) short soft-start duration or (ii) output overload or (iii) output short-circuited.
17 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information overload / short-circuit protection each current limit comparator in the SC2440 limits the peak inductor current to 2.6a. the regulator output voltage will fall if the load is increased above the current limit. if overload is detected (the output voltage falls below 74% of the set voltage), then the regulator will be shut off. an internal 0.8a current sink starts to discharge the soft-start capacitor. as the soft-start capacitor is discharged below 1v, the discharge current source turns off and the soft-start capacitor is recharged with a 1.8a current source. the regulator undergoes soft-start. during soft-start (1v < v ss < 2v), the overload shutdown latch in figure 3 cannot be set. when v ss exceeds 2v, the set input of the overload latch is no longer blanked. if v fb is still below 0.74v, then the regulator will undergo shutdown and restart. the soft- start process should allow the output voltage to reach 74% of its final value before c ss is charged above 2v. figures 10(a) and 10(b) show the timing diagrams of successful and failed start-up waveforms respectively. the soft-start interval should also be made sufficiently long so that the output voltage rises monotonically and it does not overshoot its final voltage by more than 5%. when starting into a shorted output, the SC2440 will repeatedly start and shut off (?hiccup?). v ss and v comp will appear as asymmetrical triangular waves [figure 10(b)]. power good indicators the pgood pins (pins 11 and 14) are the open-collector outputs of the power good comparators. these slow comparators are incorporated with small amount of hysteresis. the fb low-to-high trip voltage of the power good comparators is 90% of the final regulation voltage. a pull-up resistor from each pgood pin to the input supply or the regulator output set the logic high level of the comparator. the power good comparator output becomes valid provided that v in is above 0.9v. in shutdown the power good output is actively pulled low. a power good pull-up resistor tied to the input will therefore increase current drain during shutdown. tying the power good pull-up resistor to the regulator output is preferred, as this will minimize the shutdown supply current. in shutdown there (b) on off SC2440 pgood1 ss1 ss2 c ss1 c ss2 pgood2 (a) SC2440 pgood1 ss1 ss2 c ss1 pgood2 c ss2 control1 control2 on off control1 on off control2 t d figure 11. sequencing the outputs by (a) delaying release of one channel relative to the other and (b) using the pgood of one channel to control the other.
18 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information is no voltage at the switching regulator output or current in the pgood pull-up resistor. if the pgood output high level (= v out ) is unacceptably low, then power good pull- up from the input or a separate power supply will be the only choice. sequencing the outputs as mentioned above, pulling either soft-start pin low with an external transistor shuts off the corresponding regulator (figure 11). releasing the soft-start pin enables that channel and allows it to start. delaying the release of the soft-start pin of one channel with respect to the other is a straightforward way of sequencing the outputs. figure 11(a) shows this method using two external transistors m 1 and m 2 . m 1 is turned off first, allowing channel 1 to start. channel 2 is then enabled after time t d . the pgood output of one channel can also be used in conjunction with the soft-start pin of the other channel to delay start of that regulator. this method is depicted in figure 11(b). ss2 is pulled low and channel 2 is kept off until channel 1 output rises to 90% of its set voltage. a drawback of this approach is that only pgood2 is available as a logic output. loop compensation figure 12 shows a simplified equivalent circuit of a step- down converter. the power stage, which consists of the current-mode pwm comparator, the power switch, the freewheeling diode and the inductor, feeds the output network. the power stage can be modeled as a voltage- controlled current source, producing an output current proportional to its controlling input v comp . its transconductance g mp is 5.7 w -1 . with the current loop closed, the control-to-output transfer function comp out v v has a dominant-pole p 2 located at a frequency slightly higher than that of the output filter pole. 1 out 1 out out 2 p c r n c v ni - = - ? w (8) where c 1 is the output capacitor, r out is the equivalent load resistance and n (depending on duty ratio, slope compensation, frequency and passive components) is usually between 1 and 2. if c 1 is ceramic, then its esr zero can be neglected as it situates well beyond half the switching frequency. the low frequency gain of the control-to-output transfer function is simply the product of power stage transconductance and the equivalent load resistance (figure 13). the transfer functions of the feedback network and the error amplifier are: power stage gmp = 5.7 w reference voltage 1v + - r5 c5 c6 ro r2 comp r1 fb c11 esr c1 r out v out v in i out - 1 gma = 280 mw - 1 v figure 12. simplified control loop equivalent circuit
19 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information ( ) ? ? ? + + ? ? ? ? ? + = 11 2 1 1 11 2 1 2 out fb c r r s 1 r sc 1 r r r v v (9) and ( ) ( ) ( ) 5 6 o 5 5 5 o ma fb comp r sc 1 r sc 1 r sc 1 r g v v + + + ? (10) provided that 6 5 c c >> and 5 o r r >> . in equation (10), c 5 forms a low frequency pole p 1 with the output resistance r o of the error amplifier and c 6 forms a high frequency pole p 3 with r 5 . using the component values shown in figure 1 for the 12v to 3.3v regulator (1.3mhz), w = w m = = - m 6 . 1 280 db 53 ce tan c transcondu gain loop open amplifier r 1 o hz 210 krads 3 . 1 pf 470 m 6 . 1 1 c r 1 1 5 o 1 p - = - = w - = - = w - mhz 0 . 1 mrads 5 . 6 pf 10 k 4 . 15 1 c r 1 1 6 5 3 p - = - = w - = - = w - bode plots of control-to-ouput, output-to-control and the overall loop gain. control-to-output transfer function is shown with two poles near half the switching frequency w s . figure 13. 2 p w 1 out c r n 5 o c r 1 1 p w 3 p w 6 5 c r 1 5 5 c r 1 1 z w c w w gain 2 s w out mp r g ? ? ? ? ? + 2 1 2 o ma r r r r g ? ? ? ? ? + 2 1 2 5 ma r r r r g n r c out 1 c w ) j ( t w out comp v v control - to - output transfer function
20 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information in addition c 5 and r 5 form a zero with angular frequency: khz 22 krads 140 pf 470 k 4 . 15 1 c r 1 1 5 5 1 z - = - = w - = - = w - the output-to-control transfer function out fb fb comp out comp v v v v v v = is also shown in figure 13. its mid- band gain (between z 1 and p 3 ) is ? ? ? ? ? + 2 1 2 5 ma r r r r g . the overall loop gain t(s) is the product of the control-to- output and the output-to-control transfer functions. to simplify ) j ( t w bode plot, the feedback network is assumed to be resistive. if the overall loop gain is to cross 0db at one tenth of the switching frequency ( 5 f 10 s c p = w = w ) at ?20db/decade, then its mid-band gain (between z 1 and p 2 ) will be n 10 r c r c n 10 out 1 s out 1 s 2 p c w = w = w w . this is also equal to ? ? ? ? ? + 2 1 2 5 ma out mp r r r r g r g . therefore n 10 r c r r r r g r g out 1 2 1 2 5 ma out mp w = ? ? ? ? ? + . re-arranging, ma mp 1 s 2 1 5 g ng 10 c r r 1 r w ? ? ? ? ? + = (11) w z1 is shown to be less than w p2 in figure 13. making 2 p 1 z w = w gives a first-order estimate of c 5 : 5 ) min ( out 1 5 nr r c c = (12) notice that r 5 determines the mid-band loop gain of the converter. increasing r 5 increases the mid-band gain and the crossover frequency. however it reduces the phase margin. an estimate of r 5 and c 5 can be obtained from (11) and (12) with n=1. the compensation is then checked by measuring the loop gain and the phase or by observing the inductor current and the output voltage during load transient. choose the largest r 5 and the smallest c 5 to give at least 45 of phase margin. the corresponding load transient should not show any ringing or excessive overshoot (see figures 14(c), 14(d), 17(b) and 17(c)). c 6 is a small ceramic capacitor (10-47pf) to roll off the loop gain at high frequency. feedforward capacitor c 11 boosts phase margin over a limited frequency range and is sometimes used to improve loop response. c 11 will be more effective if 2 1 1 r r r ? >> . example: determine the compensation components for the 1.3mhz 12v to 5v and 3.3v converter in figure 1. for both channels, 1 s mrads 2 . 8 - = w , a 2 i ) max ( out = and f 10 c 1 m = . n is assumed to be 1 in (11) and (12). for the 3.3v output: w = ? ? ? ? + = - - k 9 . 16 ) 10 8 . 2 ( ) 7 . 5 ( ) 1 ( 10 10 10 2 . 8 k 10 k 3 . 23 1 r 4 5 6 5 nf 1 ) a 2 ( k 9 . 16 ) 1 ( v 3 . 3 10 c 5 5 = = - for the 5v channel: w = ? ? ? ? + = - - k 5 . 25 ) 10 8 . 2 ( ) 7 . 5 ( ) 1 ( 10 10 10 2 . 8 k 10 k 2 . 40 1 r 4 5 6 7 nf 1 ) a 2 ( k 5 . 25 ) 1 ( v 5 10 c 5 8 = = - c 6 and c 9 (both 10pf) are then added to increase gain margin. load transient responses of both channels are observed using these values. there is very little inductor current overshoot even with c 5 and c 8 reduced to 470pf and 220pf respectively (figure 14). the measured overall loop gain and phase plots of the converter are also shown.
21 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information board layout considerations in a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry switched currents with high dt di (figure 15). for jitter-free operation, the size of the loop formed by these components should be minimized. since the power switches are already integrated within the SC2440, connecting the anodes of both freewheeling diodes close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. the input bypass capacitors should also be placed close to the figure 14. overall loop gain and phase versus frequency for (a) channel 1 and (b) channel 2 of the dual dc-dc converter in figure 1. (c) channel 1 load transient response, i out1 is switched between 0.3a and 1.7a. (d) channel 2 load transient response, i out2 is switched between 0.45a and 1.7a. upper trace : out1 voltage, ac coupled, 0.5v/div lower trace : l 1 inductor current, 0.5a/div upper trace : out2 voltage, ac coupled, 0.5v/div lower trace : l 2 inductor current, 0.5a/div (d) (c) 40 m s/div v out =5v 40 m s/div v out =3.3v (a) v in =12v, v out =3.3v at 1.7a, c 5 =470pf, r 5 =15.4k w and c 6 =10pf (b) v in =12v, v out =5v at 1.7a, c 7 =220pf, r 8 =24.3k w and c 9 =10pf
22 ? 2005 semtech corp. www.semtech.com sc2 440 power management applications information input pins. shortening the traces of the sw and boost nodes reduces the parasitic trace inductance at these nodes. this not only reduces emi but also decreases switching voltage spikes at these nodes. figures 16(a) and 16(b) shows how various external components are placed around the SC2440. the frequency-setting resistor is placed next to the rosc pin on the backside. the resistor is grounded to the ground plane, which is then tied to anodes of the freewheeling diodes with vias. these precautions reduce switching noise pickup at the rosc pin. to ensure proper adhesion to the ground plane, avoid using vias directly under the device. in figure 15 two 12mil vias are placed at the edge of the underside pad. in v out v l z fast switching current paths in a buck regulator. minimize the size of this loop to reduce parasitic trace inductance. figure 15. suggested pcb layout for the SC2440. notice that there is no via directly under the device and that the only component on the backside is the frequency-setting resistor. all vias are 12mil in diameter. figure 16. (a) r9 gnd r9 gnd (b) gnd vin c2 l2 d3 l1 c4 d4 d1 d2 c15 c1 c3 r3 r4 c9 c8 r7 r8 c7 r6 c6 c5 r5 r2 r1 vout2 vout1 vin or vout2 vin or vout1 gnd u1 c10 gnd gnd vin c2 l2 d3 l1 c4 d4 d1 d2 c15 c1 c3 r3 r4 c9 c8 r7 r8 c7 r6 c6 c5 r5 r2 r1 vout2 vout1 vin or vout2 vin or vout1 gnd u1 c10 gnd
23 ? 2005 semtech corp. www.semtech.com sc2 440 power management typical application circuits c15 4.7 m f r3 8.06k SC2440 gnd ss2 in sw1 fb2 rosc comp2 c9 22p f r7 13.4k boost1 c1 10 m f boost2 sw2 l1 1.4 m h c2 0.1 m f l2 1.8 m h c4 0.1 m f pgood2 ss1 pgood1 comp1 fb1 c3 20 m f d1 ups120 d2 ups120 r8 100k r6 100k r9 15k out1 3.3v/2a 10k r4 10k r2 r1 23.2k c7 22n f c10 22n f c8 390p f r5 15.4k c5 390p f d4 1n4148 sync l1 & l2: sumida cr43 out2 1.8v/2a d3 1n4148 vin 5v figure 17(a). 1.3mhz 5v to 3.3v and 1.8v step-down converter figures 17(b) and 17(c). load transient response. i out is switched between 0.3a and 1.75a. 20 m s/div upper trace : out1 voltage, ac coupled, 0.2v/div lower trace : l 1 inductor current, 0.5a/div (b) out1 20 m s/div upper trace : out2 voltage, ac coupled, 0.2v/div lower trace : l 2 inductor current, 0.5a/div (c) out2 efficiency vs load current 50 55 60 65 70 75 80 85 90 95 0 0.5 1 1.5 2 load current (a) efficiency (%) v out2 = 1.8v v out1 = 3.3v v in = 5v
24 ? 2005 semtech corp. www.semtech.com sc2 440 power management typical application circuits c15 4.7 m f SC2440 gnd ss2 in sw1 fb2 rosc comp2 c9 10p f r7 11.8k boost1 c1 10 m f boost2 sw2 l1 1.8 m h c2 0.1 m f l2 1 m h c4 0.1 m f pgood2 ss1 pgood1 comp1 fb1 c3 22 m f d1 ups120 d2 ups120 r8 100k r9 12.1k out1 2.5v/2a 4.02k r11 r3 8.06k 20k r2 r1 30.1k c7 22n f c10 22n f c8 470p f r5 14.7k c5 470p f d4 1n4148 sync l1 & l2: sumida cr43 out2 0.8v/2a d3 bat - 54 vin 5v c6 10p f 30.1k r10 figure 18(a). producing an output lower than fb voltage. 1.5mhz 5v to 2.5v and 0.8v step-down converter r 3 is a pre-load to shunt the current from r 10 and r 11 before pgood1 releases ss2. figure 18(b). v in start-up transient (i out1 = i out2 = 1a). 2ms/div ch1 ch2 ch3 ch4 load regulation -2.0 -1.5 -1.0 -0.5 0.0 0.0 0.5 1.0 1.5 2.0 load current (a) percentage deviation (%) ch1 : out1 voltage, 0.5v/div ch4 : pgood2, 1v/div ch2 : out2 voltage, 1v/div ch3 : ss2 voltage, 1v/div out1 out2
25 ? 2005 semtech corp. www.semtech.com sc2 440 power management typical application circuits c16 1 m f r3 40.2k SC2440 gnd ss2 in sw1 fb2 rosc comp2 c9 10p f r7 11.8k boost1 c1 10 m f x 2 boost2 sw2 l1 15 m h c2 0.1 m f l2 6.8 m h c4 0.1 m f pgood2 ss1 pgood1 comp1 fb1 c3 d1 ups140 d2 ups140 r8 100k r6 100k r9 51.1k out1 5v/2a 49.9k r4 51.1k r2 r1 205k c7 33n f c10 33n f c8 4.7n f r5 22.1k c5 2.2n f d4 1n4148 sync l1 : coiltronic dr74 out2 1.8v/2a d3 1n4148 vin 20v l2 : coiltronic dr73 10 m f x 2 c13 68p f c12 10p f c11 33p f c6 10p f c15 47 m f c15 : 25v electrolytic all other capacitor are ceramic. figure 19(a). 540khz 20v to 5v and 1.8v step-down converter. notice that channel 2 is bootstrapped from out1. this bootstrapping scheme requires out1 to be present at all times (i.e. no hiccup or shutdown). channel 2 will still run if out1 is absent. however its power disspation will be high. 1 m s/div ch1 : sw1 voltage, 10v/div ch2 : sw2 voltage, 10v/div figure 19(b). switching waveforms. v in = 20v i out1 = 1a i out2 = 1a ch1 ch2 4ms/div upper trace : v in , 10v/div middle trace : v out1 , 2v/div lower trace : v out2 , 1v/div figure 19(c). v in start up transient. i out1 = i out2 = 1.5a.
26 ? 2005 semtech corp. www.semtech.com sc2 440 power management outline drawing - tssop-16 w/edp land pattern - tssop-16 w/edp (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. inches dimensions z p y x dim c g millimeters f .126 3.20 f f l (l1) c 01 gage plane see detail detail a a 0.25 .026 bsc .252 bsc 16 .004 .169 .193 .173 .197 .007 - 16 0.10 0.65 bsc 6.40 bsc 4.40 5.00 - .177 .201 4.30 4.90 .012 0.19 4.50 5.10 0.30 bxn 2x n/2 tips seating aaa c e/2 indicator pin 1 2x 1 3 2 n a a2 a1 e1 bbb c a-b d ccc c dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view (.039) .004 .008 - .024 - - - - 0 .018 .003 .031 .002 - 8 0 0.20 0.10 - 8 0.45 0.09 0.80 0.05 .030 .007 .047 .042 .006 - (1.0) 0.60 - 0.75 0.20 - - - 1.20 1.05 0.15 a b c d e e/2 h plane d reference jedec std mo-153, variation ab. 4. inches b n ccc aaa bbb 01 e1 e l l1 e d c a2 a1 dim a min max millimeters min dimensions nom max nom e f .118 3.00 2.85 .122 3.10 bottom view exposed pad f f .112 semtech corporation power management products division 200 flynn road, camarillo, ca 93012-8790 phone: (805)498-2111 fax (805)498-3804 contact information

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